uni soni c technologi es co., ltd L8002 preliminary cmos ic www.unisonic.com.tw 1 of 6 copyright ? 2017 unisonic technologies co., ltd qw-r502-b55 .a fet bi as con t roller ? descri pt i on the utc L8002 is specially designed integrated circuit for satellite receiver front-end block. it provides stable drain and gate bias conditions for gaas or hemt fets. the utc L8002 , provide six fets bias control respectively. by adjusting two internal resistor s, it can change the fets bias current to optimize the sate llite receiver front end block performances. it generates the required negative voltage to bias the gate of gaas fet, and internally provides protection circuit that can protect the fet devices during su pply voltage transient. so it is very popular in satellite receiver front end block. ? feat u res * built in fet device protection circuit * stable bias control for gaas and hemt fets * drive up to six fets * 2.5v supply voltage ? orderi n g i n form at i on ordering number lead free halogen free package packing L8002l-r20-r L8002g-r20-r ssop-20 tape reel ? m ark i n g
L8002 preliminary cmos ic u n i son i c t ech n ologi es co., lt d 2 of 6 www.unisonic.com.tw qw-r502-b55 a ? pi n con fi gu rat i on 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 vd1 vg1 vd2 vg2 vd3 vg3 gnd nc cnb1 cnb2 csub nc nc vg6 vd6 vg5 vd5 vg4 vd4 v cc ? pi n descri pt i on pin no. pin name description 1 vd1 1 st drain output voltage 2 vg1 1 st gate output voltage 3 vd2 2 nd drain output voltage 4 vg2 2 nd gate output voltage 5 vg3 3 rd gate output voltage 6 vd3 3 rd drain output voltage 7 gnd ground 8 nc no connect 9 cnb1 osc output 10 cnb2 rectifier input 11 csub negative voltage output 12 nc no connect 13 nc no connect 14 vg6 6 th gate output voltage 15 vd6 6 th drain output voltage 16 vg5 5 th gate output voltage 17 vd5 5 th drain output voltage 18 vg4 4 th gate output voltage 19 vd4 4 th drain output voltage 20 v cc supply voltage
L8002 preliminary cmos ic u n i son i c t ech n ologi es co., lt d 3 of 6 www.unisonic.com.tw qw-r502-b55 a ? block di agram
L8002 preliminary cmos ic u n i son i c t ech n ologi es co., lt d 4 of 6 www.unisonic.com.tw qw-r502-b55 a ? absolu t e m ax i m u m rat i n g parameter symbol ratings unit supply voltage v cc -0.6 ~ 3 v supply current i cc 100 ma maximum drain current i d 15 ma maximum c sub sink current i csub -500 ua operating temperature t opr -40 ~ +85 c storage temperature t stg -50 ~ +125 c note: absolute maximum ratings are those values beyond which the device could be permanently damaged. absolute maximum ratings are stress ratings only and functional device oper ation is not implied. ? elect ri cal ch aract eri st i cs (v cc =2.5v, i d =9.5ma, t a =25c, unless otherwise stated) parameter symbol test conditions min typ max unit supply voltage v cc 2.375 2.5 2.625 v supply current i cc no fet 6 10 ma i sub =0ua, v cc =2.5v -2 -1 v negative voltage v sub i sub =-200ua -1 v oscillator freq. f o 300 450 800 khz drain current i d 8 9.5 12 ma drain current change with v cc ? i dv v cc =2.375v~2.625v 2 %/v vd1/vd2/vd3/vd4/vd5/vd6 drain offset current ? i dc 0.5 ma drain current change with temp. ? i dt t=-40~85c 0.5 %/c drain voltage v d i d =9.5ma 1.8 2 2.2 v drain voltage change with v cc ? v dv v cc =2.375v~2.625v 0.5 %/v drain voltage change ? v dt t=-40~85c 100 ppm/c dynamic gate voltage range v g csub without loading -2 0.7 v drain output noise voltage v dn with drain bypass capacitor=10nf 0.05 v pp gate output noise voltage v gn with gate bypass capacitor=10nf 0.03 v pp
L8002 preliminary cmos ic u n i son i c t ech n ologi es co., lt d 5 of 6 www.unisonic.com.tw qw-r502-b55 a ? t y pi cal appli cat i on ci rcu i t there are three major functions provided by utc L8002 : support negative voltage, bias control circuit, and fet protesting circuit. the negative voltage is generated us ing internal oscillator. it only needs an ac coupled capacitor c nb 47nf and a negative voltage bypass capacitor c sub 47nf. the utc L8002 devices have been designed to protect the external fets from adverse operating conditions. with a jfet connected to any bias circuit, the gate output voltage of the bias circui t can not exceed the range -2v to 0.7v, under any conditions including powerup and powerdown transients. should the negativ e bias generator be shorted or overloaded so that the drai n current of the external fets can no longer be controlled, the drain supply to fets is shut down to avoid damage to the fets by excessive drain current. the following diagrams show the L8002 in typical lnb applications. within each fet gain stage the num bering system indicates how the bias stages relate to the application circuits.
L8002 preliminary cmos ic u n i son i c t ech n ologi es co., lt d 6 of 6 www.unisonic.com.tw qw-r502-b55 a ? t y pi cal appli cat i on ci rcu i t utc assumes no responsibility for equipment failures that result from u sing products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition rang es, or other parameters) listed in products specifications of any and all utc products described or contained herein. utc products are not designed for use in life support appliances, devices or s ystems where malfunction of these products can be reasonably expected to result in personal injury. r eproduction in whole or in part is prohibited without the prior written consent of the copyright owner. t he information presented in this document does not form part of any quotation or contract, is believe d to be accurate and reliable and may be changed without notice.
|
